1. Field of the Invention
The present invention relates to a technology for supporting logic verification of a large scale integration (LSI).
2. Description of the Related Art
Logic verification to check if an LSI operates normally is imperative in designing the LSI. There is a growing demand for an LSI of greater scale, higher performance, higher speed, and less power consumption, and for such LSI, the logic verification is especially important to maintain the quality. Meanwhile, there also is an increasing demand for improving the efficiency of the verification by shortening a verification period.
FIG. 1 is a schematic of a conventional verification system. According to the verification system 3700, review information 3703 and a verification property 3704 are produced from a specification 3701 of a target circuit, which is made by a designer, thorough a manual conversion process 3702 executed by the designer. The review information 3703 is fed back to the specification 3701 to review the specification 3701.
The verification property 3704 obtained through the conversion process, a verification scenario 3705, and circuit information 3706 of the target circuit, are input into a verification apparatus 3710 to perform logic verification of the target circuit. Conventional techniques related to such a verification system have been disclosed in: Japanese Patent Application Laid-Open Publication No. 2000-181939; Japanese Patent Application Laid-Open Publication No. 2003-30270; and Japanese Patent Application Laid-Open Publication No. 2005-196681.
However, in performing logic verification of a state saving module such as a register in a logic circuit, it is necessary to produce a great number of verification properties which are used to monitor each register rewriting condition read out of a specification and to report an error if any. The verification properties have orders of priority, and producing the verification properties in consideration of the priority order without an error is extremely difficult.